1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular to a metal-oxide-semiconductor field effect transistor (MOSFET) device.
2. Description of the Background Art
Referring to FIG. 1a, a first insulation layer 5, a first polycrystal silicon layer 7, a first silicide layer 8 and a second insulation layer 10 are sequentially formed on a semiconductor substrate 1 which is divided into an active region A and an isolation region B by a field oxide film 3. Next, an photoetching process using a photoresist film (not shown) is performed thereon, thereby forming a gate 12.
Thereafter, a thermal oxidation process is carried out in order to protect the side portions of the first polycrystal silicon layer 7 and the first silicide layer 8 of the gate 12 which are exposed during the photoetching process. As a result of the thermal oxidation process, a thin oxide film (not shown) is formed at the side portions of the gate 12 and the upper portion of the semiconductor substrate 1.
Here, the first silicide layer 8, the first polycrystal silicon layer 7, the first insulation layer 5 and the second insulation layer have a different thermal expansion coefficient, and thus the first silicide layer 8 is considerably shrunken during a cooling process after the thermal oxidation process, as compared with the first polycrystal silicon layer 7 and the second insulation layer 10, thereby forming a shape as shown in FIG. 1a. Next, an impurity is implanted into the upper portion of the semiconductor substrate 1 which is adjacent to the gate 12 according to a self-aligned process using the gate 12 as a mask, thereby forming a first impurity region 14a and a second impurity region 14b which serve as a source or drain.
As illustrated in FIG. 1b, a third insulation layer 16 consisting of a nitride is formed at the upper and side portions of the gate 12, and the upper portion of the semiconductor substrate 1. Here, the third insulation layer 16 is formed along the winding of the side portions of the gate 12. A fourth insulation layer 18 consisting of an oxide is formed on the third insulation layer 16. As the fourth insulation layer 18 is formed, it raps around and touches itself before completely filling the holes between the gates 12. Accordingly, gaps 20 are formed between the gates 12, as shown in FIG. 1c.
Referring to FIG. 1d, the fourth insulation layer 18 and the third insulation layer 16 are sequentially partially etched in accordance with the photoetching process using a photoresist film (not shown), thereby forming a first contract hole 19 in order for the first impurity region 14a to be exposed. Thereafter, a second polycrystal silicon layer is deposited in the first contact hole 19 and on the fourth insulation layer 18. A storage node contact plug 22 is formed in the first contact hole 19 by performing a chemical mechanical polishing process (CMP) until the upper portion of the fourth insulation layer 18 is exposed. The storage node contact plug 22 serves to electrically connect the first impurity region 14a to a storage node contact (not shown) of a capacitor. A fifth insulation layer 24 is formed on the whole surface of the semiconductor.
As illustrated in FIG. 1e, the fifth insulation layer 24, the fourth insulation layer 18 and the third insulation layer 16 are sequentially partially etched according to the photoetching process using a patterned photoresist film (not shown), thereby forming a contact hole 23 so that the second impurity region 14b can be exposed. Thereafter, a third polycrystal silicon layer 26 and a second silicide layer 28 are sequentially deposited and patterned, thus forming a bit line 30.
In the above-described metal-oxide-semiconductor field effect transistor (MOSFET) device, a path consisting of the gaps 20 between the adjacent gates 12 is formed in a longitudinal direction of the gate 12. Accordingly, after the first and second contact holes 19, 23 are formed at a predetermined portion between the gates 12, when the storage node contact plug 22 or the bit line 30 is formed in the first and second contact hole 19, 23, the polycrystal silicon flows into and fills the path consisting of the gaps.
FIG. 2 is a scanning electron microscope (SEM) photograph showing a state where the polycrystal silicon flows into the path consisting of the gaps. As shown therein, the polycrystal silicon filled in a contact hole 40 flows into and fills the path consisting of the gaps, thereby making adjacent contacts 44a, 44b short.
FIGS. 3a and 3b illustrate a conventional method for overcoming the aforementioned disadvantage.
After the processes as shown in FIGS. 1a to 1c are carried out, as shown in FIG. 3a, the fourth insulation layer 18 and the third insulation layer 16 are sequentially partially etched according to the photoetching process using a photoresist film (not shown), thereby forming the first contact hole 19. A nitride layer is formed in the first contact hole 19 and on the fourth insulation layer 18, and an anisotropic etching process is performed thereon without a mask, thereby forming a sidewall spacer 60a at the side portions of the first contact hole 19. As illustrated in FIG. 3b, in a method for forming the bit line 30, a sidewall spacer 60b is formed at the side portions of the second contact hole 23 according to a process corresponding to the process as shown in FIG. 3a. The sidewall spacer 60a, 60b serves to block an entrance (or an exit) of the path consisting of the gaps, and thus prevent a second polycrystal silicon layer and a third polycrystal silicon layer which are formed according to a succeeding process from flowing into the path.
However, it is difficult to determine the conditions of the anisotropic etching process for forming the sidewall spacer 60. In case the etching process is excessively performed, the sidewall spacer cannot block the entrance (or exit) of the path consisting of the gaps formed at the side portions of the contact hole. To the contrary, when the etching process is deficiently carried out, the nitride layer which is deposited so as to form the sidewall spacer covers the upper portion of the semiconductor substrate 1 which is exposed due to the contact hole. Accordingly, the storage node contact plug 22 or the bit line 30 cannot be contacted with the impurity regions 14a, 14b operated as a source/drain. Even if the conditions of the anisotropic etching process are properly made, and thus the sidewall spacer blocks the entrance (or the exit) of the path consisting of the gaps formed at the side portions of the contact hole, and simultaneously the storage node contact plug 22 or the bit line 30 is contacted with the source/drain regions 14a, 14b, a contact area of the storage node contact plug 22 or the bit line 30 and the source/drain regions 14a, 14b by the sidewall spacer 60a, 60b is decreased, and as a result, a contact resistance is increased.